SoC Performance Modeling Opportunities at Apple

United States


Role Number:200545435
Do you have an uncommon desire to learn how every smallest detail works in electronic devices? Do you believe that truly meaningful innovation is the result of going after the most complex problem rather than the easy ones? Do you love to conquer difficult challenges both in your work life and your personal life with your grit and uncanny creativity? We do! We are seeking a highly ambitious engineer to join our group that is driving the architecture of the next-generation of Apple silicon. The SoC architecture and performance team works with various hardware, software, and machine learning groups to help design, optimize, and ship our industry-leading chips powering iPhone, Apple Watch, Vision Pro, iPad, Macs, and more! You’ll join a team of highly experienced performance modelers and SoC engineers who deeply analyze the ways our chips are used and drive architecture innovation for Apple’s future silicon. If you have a passion to develop simulation models, analysis tools, and machine learning techniques to bring new ideas to life, join us and help raise the bar even higher on the performance, power efficiency, and hardware/software integration of Apple’s products! The team has offices in Cupertino, CA, San Diego, CA, Beaverton, OR, Austin, TX, and Cambridge, MA.


Below are the various areas you can explore within Platform Architecture SoC Performance: SoC Memory Performance: Our group focuses on balancing the performance and power of the memory system across all Apple products. The work includes the detailed modeling of Apple memory controllers for different memory technologies, microarchitecture fine tuning, and architectural exploration of future memory technologies. The role in this group has close collaboration with CPU, GPU, ML, and SoC architects and design teams. Experience with power modeling in addition to performance, and/or prior work on memory controller scheduler is a plus. SoC Cache Performance: Our group is building and maintaining the simulation models for the cache architecture in Apple’s SoCs. We deeply analyze how real-world applications use the memory system to develop a better caching architecture for CPU, GPU, ML, Display, Camera, etc., and we use our modeling to provide guidance for future products on the optimal cache architecture, policy trade-offs and technology direction. We are looking for engineers who have a deep passion for creating hardware models at both higher levels and the detailed design level, and are enthusiastic about innovating new ways to make our caches more effective, including machine learning techniques. SoC QoS Performance: The engineers on this team solve challenging problems in the area of quality-of-service (QoS) and use case performance. SoC going into Apple devices has dozens of IPs. The IPs share resources such as fabric, system cache and DRAM, but their performance requirements differ and vary from low latency, high bandwidth to real time with deadline. The team is responsible for defining the requirements and ensuring to build SoC architecture and design which satisfy them, by using (and developing) SoC-level performance simulators with future looking use cases or Silicon traces or a mix of the two. The work is done through close collaboration with the other SoC architects, IP, design, and Silicon teams. SoC Performance Validation: This group drives the performance and quality-of-service analysis and validation for the SoCs that form the heart of Apple products like the Apple Watch, iPhone, iPad, MacBook, and Vision Pro products, to ensure that the next Apple silicon will flawlessly meet all the performance requirements. Our group leverages both analytical and event-driven models, and we build and maintain the pipelines for automated simulation, data collection, processing, and analysis. We work closely with architecture, design, and silicon teams to deliver this mission-critical work. We look for individuals who enjoy being in a highly cross-functional role and are not shy to question the status quo and push for innovation.

Minimum Qualifications

Key Qualifications

  • Experience in using and writing SoC performance models, and transforming the simulation results into compelling performance analysis.
  • Excellent coding skills in C++ and Python.
  • Knowledge in one or more of the following domains: Cache architecture, DRAM controllers, NoC topologies, QoS/realtime and coherency protocols.
  • Enthusiasm to work with domain experts from CPU, GPU, ML, Camera teams to translate their performance/power requirements into model studies that drive architecture and design decisions.

Preferred Qualifications

Education & Experience

Some of the relevant degrees include: Computer Engineering, Computer Science, Electrical Engineering, or related

Additional Requirements

  • You will enjoy being a part of our team if:
  • You derive satisfaction from not only performing the analysis, but using your interpersonal skills and your data to influence the direction of the organization.
  • You enjoy doing deep-dives into hardware and software parts that are outside of your immediate area of responsibility, and use the learnings to innovate the parts you own.

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.