Physical Design Verification Engineer
Imagine what you could do here at Apple? Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish.
We searching for a self-motivated engineer for the role of ASIC physical verification engineer. You will engage with forefront technology nodes to build outstanding custom silicon designs used to connect our extraordinary products to the world as well as optimizing their performance. You will join a development team that values engineering excellence, creativity and innovation. You will become a valuable member of Apple's Japan Design Centre.
Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you help us design next revolutionary Apple products?
- As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level.
- Collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
- Work on padring, bump, RDL design, and working with the package and floorplan teams.
- Work on place & route, CTS, timing convergence
- Drive optimization of PnR partitions, to achieve best Power/Performance/Area.
- We are looking for experienced applicants with strong understanding of the RTL2GDSII flow and concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
- Typically requires more than 5 years of relevant industry experience.
- Strong knowledge of physical verification flows and methodology.
- Knowledgeable in partition level P&R implementation, including floorplanning, clock and power distribution, timing closure, physical and electrical verification.
- Knowledge of all aspects of Analog mixed signal physical design.
- Scripting skills to debug flow related issues and make enhancements as appropriate.
- Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
- Real chip tapeout experience with a track record of successful signoff.
- Excellent interpersonal skills and able to work with multi-functional teams.
- English communication with e-mail is required.
- Custom layout design background and experience a plus.
- Hands-on experience with ECO implementation, both functional and timing closure is helpful.
- Familiar with tapeout of partitions and Verification Flows like LEQ, IR/EM and DFM closure is preferred.
- Verbal communication in English is considered a plus.
- Bachelors of Science, preferred in Electrical Engineering.