Analog Layout Engineer - Power Management

Munich, Bavaria-Bayern, Germany
Hardware

Summary

Posted: 24. Oct 2018
Role Number: 200002468
ANALOG LAYOUT ENGINEER – POWER MANAGEMENT Will you help us design future generations of revolutionary Apple products? The Silicon Engineering team is seeking an Analog Layout Engineer with a strong foundation in custom analog layout and a real passion for building new technologies. At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented Layout Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. You will be responsible for the Layout and verification of Analog IP and the support of toplevel layout of Power Management products for battery operated portable devices.

Key Qualifications

  • We would be interested in meeting you if you have proven expertise in the following areas:
  • - Several years of experience in custom analog layout with extensive knowledge on deep sub-micron CMOS (40nm, 28nm, etc.)
  • - Capability to lead other layout engineers for top-level integration.
  • - Knowledgeable on layout techniques for device matching, minimizing parasitics and high power routing.
  • - You understand issues of RC delay, electromigration, and cross capacitance
  • - Experience with Power Management circuit layout would be an asset
  • - Must recognize failure prone circuit and layout structures, dedicatedly work with circuit designer for best approach to problems
  • - High level proficiency in interpretation of Calibre DRC, ERC, LVS, etc.
  • - Knowledge of Cadence Layout tools
  • - Scripting skills in PERL or SKILL or AMPLE are considered a plus, but not required
  • - Excellent interpersonal skills and able to work with multi-functional teams

Description

- Detailed transistor level layout of analog circuit blocks - Block level and top-level layout through full verification flow including RCLK extraction, DRC, LVS, and DFM checking - Co-work with designers on block level and top-level floorplanning incl. area and effort estimate - Execute peer reviews for critical and major layout blocks. - Layout according to DFM rules - Top-level layout integration and verification - Schedule management and tracking

Education & Experience

- MS in Electrical Engineering required or equivalent, alternatively equivalent experience Apple is an Equal Opportunity Employer committed to inclusion and diversity. We take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities.

Additional Requirements