Physical Design Engineer - Power Management

Munich, Bavaria-Bayern, Germany


Posted: 24. Oct 2018
Role Number: 200002525
Will you help us design future generations of revolutionary Apple products? The Silicon Engineering team is seeking a Physical Design Engineer with a strong foundation in digital and Mixed signal products and a real passion for building new technologies. At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented Physical Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. You will be responsible for the Physical Design of digital part of Power Management products for battery operated portable devices.

Key Qualifications

  • We would be interested in meeting you if you have proven expertise in the following areas:
  • - Several years of Physical Design experience on digital and Mixed signal products
  • - Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route
  • - Experience in developing and implementing Power-grid and Clock specifications
  • - Solid Understanding of all aspects of Physical construction, Integration and Physical Verification
  • - Working knowledge of basic Power Management Architecture would be an asset
  • - Power user of industry standard Physical Design & Synthesis tools
  • - Solid Understanding of scripting languages such as Perl/Tcl
  • - Working knowledge of Extraction and STA methodology and tools
  • - Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
  • - Excellent communication skills and able to work with cross-functional teams


- Generate block level static timing constraints. - Create block floor-plan including pin placement, partitions and power grid. - Develop and validate high performance low power clock network guidelines. - Perform block level place and route and close the design to meet timing, area and power constraints. - Generate and Implement ECOs to fix timing, noise and EM IR violations. - Run Physical design verification flow at block level and provide guidelines to fix LVS/DRC violations to other designers. - Participate in establishing CAD and physical design methodologies for correct by construction designs. - Assist in flow development for chip integration. - Schedule management and tracking

Education & Experience

- MS in Electrical Engineering required or equivalent, alternatively equivalent experience Apple is an Equal Opportunity Employer committed to inclusion and diversity. We take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities.

Additional Requirements