CAD Engineer - PDV & Extraction

Munich, Bavaria-Bayern, Germany


Posted: 24. Oct 2018
Role Number: 200002555
Will you help us design future generations of revolutionary Apple products? The Silicon Engineering team is seeking a CAD Engineer with a strong foundation in PDV and Extraction and a real passion for building new technologies. At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented CAD Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. You will be responsible for developing, maintaining and enhancing physical design verification (PDV) and extraction flows. Working with the CAD team you will be developing flows methodologies for different tech nodes and interfacing with custom digital, analog and ASIC design teams. We look for someone with good understanding of DRC/LVS runsets, writing from scratch and/or modify existing ones. Experience with the Design for Manufacturability (DFM) rules at different geometries a definite plus. You will use your experience in parasitic extraction to develop /define/ refine extraction and simulation methodologies for transistor as well as gate level designs (capacitance modelling, interconnect parasitic extraction, RC reduction, validation of RC results in field solver, etc.)

Key Qualifications

  • - Typically requires 5+ years of industry experience in chip design process
  • - Very efficient programming capabilities in Perl, TCL, C, Makefile
  • - Expert in Calibre or Hercules/ICV runset programming for DRC/LVS/ERC rules
  • - Different technology nodes tapeout experience required
  • - Extraction flows using StarRC XT/QRC/ XRC for transistor level as well as gate level LVS flows
  • - Device extraction as well as Capacitance Extraction experience is a plus
  • - Field solver packages would be a plus
  • - RC reduction tools is a plus
  • - Experience in working with international teams


- Develop, maintain and enhance flows for all aspects of physical design verification and extraction - Coordinate effort of validating the flows, enhancing for custom checks and data generation. - Interacting the design team and PD teams to facilitate the chip design process - Familiar with the Electrical rule checks and Programmable ERCs - Work closely with various design groups on their extraction requirements for various post layout flows

Education & Experience

- MS in Electrical Engineering required or equivalent, alternatively equivalent experience Apple is an Equal Opportunity Employer committed to inclusion and diversity. We take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities.

Additional Requirements