Formal Verification Engineer

Munich, Bavaria-Bayern, Germany
Hardware

Summary

Posted: 24. Oct 2018
Role Number: 200002578
Imagine what you could do here. At Apple, new ideas have a way of becoming outstanding products, services, and customer experiences quick. Bring passion and dedication to your job, and there's no telling what we could accomplish together. Are you demonstrating in-depth understanding of formal tools, such as Jasper, Jasper Gold, IFV, etc.? Are you an expert and holder of advanced knowledge of CPU, SOC or GPU design architectures, VLSI circuits, and digital logic design? As the Formal Verification Engineer you will be responsible for the pre-silicon RTL verification utilizing formal and property checking methods. This includes deep understanding of the micro-architectural details of their block and how it works within the broader design. We will use your strong computer architecture background, and a proven foundation in verification methodology to close testing coverage with high confidence. Every single day, we do amazing things at Apple. Do you want to impact billions of users by developing extraordinary products with a prime focus on accuracy and performance of the product? You will become part of a hands-on development team that furthers engineering excellence, creativity and innovation. Dynamic, inspiring people and innovative technologies are the norm here. We want you to join our team if you are an innovative engineer with the dream to research and develop solutions that do not yet exist.

Key Qualifications

  • - Your practical experience in abstraction techniques, formal verification technologies and analysis of pipelined micro-architectures, MMU’s, and cache coherency control mechanisms is much desired
  • - We will need to be confident in your mastery of reviewing and interpreting hardware specifications
  • - By now you have strong familiarity with HDL's such as Verilog / System Verilog and temporal logic assertion-based languages such as SVA
  • - You have hands-on experience in using EDA formal verification tools
  • - Your knowledge of constrained random verification methods is a huge plus for us

Description

- We expect you to work with the design team to review and improve hardware specifications - You will develop verification plans in coordination with design leads and architects - You will also develop and work towards closure of formal verification proofs across multiple design blocks - You are going to focus on conducting formal verification reviews and review formal proofs with design and verification teams - You will create automated verification flows for block verification - You are going to work with other block and core level engineers to ensure seamless verification flow

Education & Experience

Master's in Electrical / Computer Engineering, or equivalent strong experience required. Apple is an Equal Opportunity Employer committed to inclusion and diversity. We take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities.

Additional Requirements