RFIC Design Engineer

Munich, Bavaria-Bayern, Germany
Hardware

Summary

Posted: 14. Mar 2019
Role Number: 200024524
Do you have a passion for crafting entirely new solutions? Do you love building without precedent? As part of our Silicon Engineering group, you’ll take imaginative and revolutionary ideas and resolve how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if need be. Join us, and you’ll help design integrated circuits that allow us to bring customers experiences they’ve never before imagined. In this highly visible role, you will be at the center of a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly.

Key Qualifications

  • The ideal candidate will have 7+ years of RF/analog and mixed-signal design experience, with 4+ years in cutting-edge RF CMOS design.
  • Direct experience designing and bringing into high volume production RF transceivers in deep sub-micron RFCMOS technology. This includes design of on-chip LNAs and PAs, PLL/VCO/LO blocks, up-conversion/down-conversion mixers, baseband filters, data converters and calibration methods associated with high performance wireless systems and ZIF designs. Experience should also include understanding of DFT and DFM techniques for high volume production environment.
  • Extensive knowledge of all or many of the following fields:
  • Deep understanding of 3GPP system specifications, able to work with system architects to translate system requirement into circuit requirement at IC level; Requires strong understanding of impact of modulation type to radio architecture and building block requirements;
  • Deep understanding of various RF transceiver architectures and their trade-offs; Demonstrate the capability to work with digital design group for an optimum partition between digital and analog domain;
  • Deep understanding of fundamentals of RF CMOS implementation, and basic building blocks, including LNAs, mixers, VCOs and DCOs, LO and PAs;
  • Deep understanding of RF device modeling, including but not limited to device noise parameters, inductor modeling; Insights into packaging effects, supply isolation, high frequency ESD structures, and circuit layout techniques for optimum RF performance;
  • Deep knowledge of de-sense and able to work closely with board RF/HW/Antenna teams to optimize board/module layouts for de-sense mitigation; Also, has experience with de-sense mitigation with integrated PMUs/DSPs (i.e. substrate isolation, return loops, package isolation, frequency planning, etc);
  • Deep understanding of mix signal mode verification methodologies such as SystemVerilog, AMS, Nanotime);
  • Deep understanding of EM tools such as EMX, HFSS;
  • Extensive experience in Si characterization and debug.

Description

As an RFIC designer, you will responsible for designing RFIC blocks/sub-systems for wireless SoC (in wireless standards such as cellular 4G/5G/mmW, WiFi/BT, etc.). Responsibilities include: - Collaborate with RF and PHY systems teams to partition system requirements and optimize RF and baseband circuit performance, power, and area. - Develop novel RFIC circuits and architectures, taking designs from concept all the way to production. - Work closely with integration/verification teams to model and verify top-level radio functionality and performance during pre-silicon phase. - Work with SiPi and packaging teams to predict/simulate RF de-sense and coupling mechanisms at chip-level and board level using EM tools - Perform detailed bring-up and characterization of radio blocks at IP level. Support system level integration and characterization of radio performance. - Drive RFIC/analog design reviews across Apple's wireless groups.

Education & Experience

- BSEE is required. MSEE/Ph. D is preferred Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.

Additional Requirements