Physical Design Manager
Munich, Bavaria-Bayern, Germany
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and uncommonly hardworking Physical Design Manager. As a member of our dynamic group, you will have the rare and rewarding opportunity to manage a team in crafting upcoming products that will delight and encourage millions of Apple’s customers every single day. In this role, you will be managing a team of engineers in an effort to collaborate with other physical design teams, CAD, timing and logic design teams, with a critical impact on implementation from netlist to tape-out.
- - You will have at least 15+ years of Physical Design experience on high PHY and/or SOC designs
- - You will have at least 5+ years of management experience and leading a team in delivering products.
- - Experience in collaborating with front-end and backend teams is a huge plus
- - Deep knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route
- - Deep understanding of Power-grid and Clock implementation methods
- - Deep Understanding of all aspects of Physical construction, Integration and Physical Verification
- - Deep knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with the logic design team for timing fixes.
- - Power user of industry standard Physical Design & Synthesis tools
- - Deep understanding of scripting languages such as Perl/Tcl
- - Extensive knowledge of Extraction and STA methodology and tools
- - Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
As a Physical Design manager, you will be involved with all phases of physical design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to leading and managing a team of engineers to see through floor-plan including pin placement, partitions, and the power grid. Develop and validate high-performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical design verification flow at chip/block level and fix LVS/DRC violations. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.
Education & Experience
Preferred Masters or Ph.D. Degree. Bachelors Degree in a technical discipline required.
- We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.