Design Verification Engineer - Graduate
Munich, Bavaria-Bayern, Germany
At Apple we believe our products begin with our people. By hiring a team with dynamic strengths, we drive creative thought. By giving that team everything they need, we drive innovation. By hiring incredible engineers, we drive precision. And through our process, we build memorable experiences for our customers. These elements come together to make Apple an amazing environment for motivated people to do the greatest work of their lives. You will become part of a hands-on development team that cultivates perfection, creativity and innovation. Will you help us design the next generation of revolutionary Apple products? In this role, you will be taking part in the design of UVM-based test-benches for memory interfaces.
- Knowledge of object oriented programming.
- Knowledge of Verilog and/or VHDL.
- Basic knowledge of memory interface protocols.
- Scripting language knowledge (perl/python).
- Should be a teammate with excellent written and verbal communication skills and have the desire to take on diverse challenges with international teams.
Responsible for ensuring the quality of the work & are expected to: - Work with the team to define and design memory models for flash memories and verification plan. - Work closely with the teams to understand and design the verification components in SystemVerilog/UVM. - Have collaborative approaches to design self-checking tests for standard compliance testing.
Education & Experience
Currently enrolled in your final year of your BSc/MSc/BEng/MEng/PhD from a reputable university.
- Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.