FrontEnd STA and Timing Constraints Development Engineer
Munich, Bavaria-Bayern, Germany
We do extraordinary things at Apple! Will you help us design future generations of revolutionary Apple products? If you are an engineer with a solid base and real passion for building new technologies and you have a consistent track record leading STA efforts for complex chip designs just imagine what you could do here at Apple. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Every single day, people do amazing things at Apple. We will change billions of users by developing extraordinary products with a prime focus on the accuracy and performance of the product. You will become part of a hands-on development team that champions engineering excellence, creativity, and innovation. Complex, encouraging people and innovative technologies are the norm here. We want you to join our team if you are an innovative engineer with the dream to research and develop solutions that do not yet exist. You will be part of the Integration team as a frontend - backend focal point for all timing and constraints development, working in advanced technologies and interacting closely both with RTL designers and Physical Designers.
- We are looking for somebody who..
- - has 3-5 years of experience in STA that includes, but not limited to responsibility for timing and constraints.
- - has extensive experience with one of the commercial STA tools.
- - understanding of DFT modes and their constraints would be an asset.
- - knowledge of noise and signal integrity effects would be nice to have.
- - experience with timing margins fundamental from synthesis to signoff.
- - skills in scripting languages (TCL, Python).
- - is familiar with the hierarchical design approach, top-down design, timing, and physical convergence.
- - has experience with design synthesis and backend STA closure.
- - understands of designs' constraints development and AC timing from specs to implementation.
- As a member of the team, you will directly develop and maintain methodology and flows related to timing verification and closure - You are going to own generation of block and full chip timing constraints - You will be working side by side with design teams to understand and debug constraints, facilitate logic changes to improve timing - In addition, you would also work with Physical Design and Logic Design teams, highlighting the STA and Timing Constraints issues and standards
Education & Experience
You hold Master's in Electrical / Computer Engineering, or equivalent strong experience.
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.