SoC Physical Design Engineer (m/f/d)

Munich, Bavaria-Bayern, Germany


Role Number:200148709
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help design the next groundbreaking Apple product. If you are eager working on challenges that no one has solved yet you will have an outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. As a classic partition PnR engineer recognized in the industry for the knowledge in standards and practices in Physical Design and having a strong background with recent successful tape-outs in deep sub-micron technology, you would perfectly fit into the team! In this position, you will take part in the large scale SoC physical design cycle from netlist to tape-out. This includes full flow of back-end implementation and verification always meeting schedule and design goals. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products?

Key Qualifications

  • We will be counting on your expertise and years of hands on experience with one of the Place & Route ('PnR') tools available today (Synopsys / Cadence). Also, you understand and use their capabilities and underlying algorithms like a pro.
  • Your knowledge with hierarchical design approach, top-down design, and timing and physical convergence
  • By now you are demonstrating in-depth understanding of static-timing analysis, extensive know-how in clock/power distribution and analysis, as well as RC extraction and correlation. You have experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration
  • You can do scripting and programming using several of the following: Perl, TCL and Make
  • We expect experience with large SoC designs (>20M gates) with frequencies in excess of 1GHZ and beyond
  • If you also have working knowledge in Verilog, that is a huge plus for us
  • Your communication skills are excellent, and like the rest of us here at Apple you love working in open and multi-cultural environment


As a member of our Physical Design team in this highly visible role, you will directly own implementation of design partition(s) (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology You are going to own block level PnR, floor-planning, clock and power distribution You will get involved with static timing closure with commercial tools You will do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC / LVS) You will be developing and validating high performance low power clock network guidelines. With great focus you will resolve design and flow issues related to physical design, and identify potential solutions whilst driving execution You know what documentation should look like, and will help with guidelines and specs

Education & Experience

You hold a degree in Electrical Engineering or equivalent experience. Apple is an Equal Opportunity Employer committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities.

Additional Requirements