Senior Analog Modelling & Verification Engineer

Munich, Bavaria-Bayern, Germany


Role Number:200158827
Join a rapidly growing team at our Munich design center. At Apple, new ideas and complex challenges have a way of becoming extraordinary products, services, and customer experiences very quickly. The AMS IP team is responsible for a wide portfolio of IPs & complete subsystems that is part of all the Apple products. In this context the Design Verification Engineer will have to collaborate with many different teams at Apple and build knowledge of many chips & platforms in order to bring system-level understanding into the verification flow. The responsibility goes end-to-end: starting at the specification level, crafting accurate behavioural models of the analog/mixed-signal blocks, executing the mixed-signal verification, doing performance analysis, and handling all the different quality metrics to signoff the verification. We are looking for an enthusiastic engineer with a strong analog design background and validated understanding of signal processing, as well as a deep foundation in modelling methodology will be used to close testing coverage with high confidence.

Key Qualifications

  • Experience of working in complex ASIC or SOC designs
  • Experience with implementation of real-numbered analog behavioral models in SystemVerilog or other HDLs
  • Experience in analog mixed signal simulations, proven understanding of UDN/UDT/UDR
  • Knowledge of analog design, understanding of AMS blocks such as Filter, opAmp, A/DPLL, ADC, DAC, SerDes, etc.
  • Experience in verification methodology (UVM/OVM) is a plus
  • Working experience with industry standard AMS design tooling(virtuosos schematic composer, ADE, HED) is an advantage
  • Knowledge of signal processing/MATLAB is helpful
  • Scripting language knowledge (perl/python)
  • Excellent communication and interpersonal skills, combined with the ability to collaborate
  • Ability to work well in an international team, take responsibility, perform under strict deadlines and motivate self and others


Use SystemVerilog, UVM and MATLAB with industry leading simulation tools and methodologies to model & verify complex mixed-signal designs from the block-level up to the SoC. Develop and verify RNM efficient and highly accurate analog behavioral models, monitors & checkers for different mixed-signal IP blocks, such as PLLs, ADCs, DACs, RF calibration blocks, and define test plans with the design team to validate the full functionality of them, as well as ensure the correct integration of the models into the verification environment. Go beyond functional verification and embed advanced performance analysis techniques as part of the verification plan. Create and maintain verification test bench components and environments. Generate directed and directed random tests & debug design and system issues. Build functional coverage points, analyze coverage, and improve test environment to target coverage holes.

Education & Experience

- Master Degree in Computer Science or equivalent

Additional Requirements

  • Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.