Design Verification Engineer - Power Management

Munich, Bavaria-Bayern, Germany
Hardware

Summary

Posted:
Role Number:200171429
Do you love working on challenges that no one has solved yet? Do you like changing the game? At Apple, we believe our products begin with our people. By hiring a team with dynamic strengths, we drive creative thought. By giving that team everything they need, we drive innovation. By hiring incredible engineers, we drive precision. And through our process, we build memorable experiences for our customers. These elements come together to make Apple an amazing environment for motivated people to do the greatest work of their lives. You will become part of a hands-on development team that cultivates perfection, creativity, and innovation. We have an opportunity for a results-oriented and exceptionally hardworking Design Verification Engineer. As a member of our multifaceted group, you will have the unique and great opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every day. We are looking for a Design Verification Engineer who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities include all phases of pre-silicon verification including establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze, and tape-out.

Key Qualifications

  • Deep knowledge of SystemVerilog and UVM
  • Experience developing scalable and portable test-benches
  • Experience with constrained random verification environments
  • Experience defining coverage space, writing coverage model, analyzing results
  • Experience with Assertion Based Verification
  • Knowledge of Object Oriented Programming
  • Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification)
  • Experience with Python, Perl or TCL
  • Excellent communication and interpersonal skills combined with the ability to collaborate
  • Basic knowledge of mixed signal verification is a plus!

Description

In this role, you will develop verification plans in coordination with design leads and architects. You'll be responsible for planning, building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Create functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip-level verification. You will use your knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a flawless verification flow.

Education & Experience

You hold a Master of Science in Electrical Engineering or Information Technology or equivalent strong experience. Apple is an Equal Opportunity Employer committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

Additional Requirements