SoC DV Lead Engineer

San Diego, California, United States
Hardware

Summary

Posted:
Role Number:200536977
Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. The SOC DV lead Engineer will be responsible for pre-silicon RTL verification of block and top level SOC at this site. With deep understanding of SOC architecture and meticulous attention to details, you will interact with all disciplines to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Key Qualifications

  • Expertise in HVL and HDL (SystemVerilog, Verilog)
  • Advanced knowledge of UVM methodology
  • Solid verification skills in problem solving, constrained random testing, and debugging
  • Knowledge of industry standard interfaces
  • Experience with System Verilog Assertion (SVA)
  • Programming experience in C
  • Experience in creating portable and reusable UVM testbenches
  • Experience writing scripts in languages such as Perl or Python
  • Experience in managing a team is a plus
  • Experience in mentoring entry level engineers
  • Adept at collaboration with Design and DV leaders with strong interpersonal skills
  • Experience defining coverage space and writing coverage model
  • Experience with low power verification is required
  • Experience with formal verification
  • Knowledge of wireless protocols like Bluetooth and WiFi is a plus

Description

- Understand details of microarchitecture and build block / chip level testbench using best-in-class verification methodology. - Create verification plan from specification and in coordination with architects. - Generate directed and ingenuous constrained random tests. - Create/analyze coverage model and enhance testbench/test to increase coverage. - Build automated flows for block and chip level verification. - Debug failures, manage bug tracking, and close coverage. - Hold detailed verification reviews and set standard for coding quality. - Work closely with team members to improve methodology and flow.

Education & Experience

BS and 10+ years of relevant industry experience

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

Pay & Benefits