Static Timing Analysis Engineer

Munich, Bavaria-Bayern, Germany


Role Number:200160285
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient hardware. You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. Every day! In this role, you are responsible for all aspects of timing including, working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure.

Key Qualifications

  • We will be counting on your expertise and years of hands-on-experience with Statical Timing analysis for high-speed chips. What we are expecting:
  • Timing of large high-performance SoC designs in sub-micron technologies is familiar to you.
  • You are proficient in STA and standards for timing closure, and have a deep understanding of noise, cross-talk, and OCV effects, among others.
  • We are looking for practical Know-How in at least one of these fields:
  • Circuit modeling, including SPICE models and worst-case corner selection.
  • Timing Margin Fundamentals from synthesis to signoff
  • You have strong programming skills with tools like Perl and/or TCL as well as with Timing Flow using industry-standard tools.
  • Experience with STA on large, complex designs and Multi-Scenario Timing Closure.
  • Familiarity with ECO techniques and implementation.
  • You are an excellent communicator who can accurately describe issues and follow them through to completion. Your attention to detail will be instrumental to success.


You will be working with design teams to understand and debug constraints, facilitate logic changes to improve timing - Working with Physical Design and Logic Design teams, highlighting issues - Help create timing ECO’s for project tapeout - We value the ability to build and maintain scripts and methodologies for analysis and runs - Document and help with guidelines and specs - Deep analysis of timing paths to identify key issues is essential - Implement timing infrastructure

Education & Experience

You hold a Master of Science in Electrical Engineering or Information Technology or equivalent strong experience. Apple is an Equal Opportunity Employer committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

Additional Requirements