Design Verification Engineer

Saint Albans, Hertfordshire, United Kingdom
Hardware

Summary

Posted: 24 Oct 2018
Weekly Hours: 35
Role Number: 200002614
Do your life’s best work here - with the whole world watching. This is a career defining opportunity to get in at the ground floor as we build our UK GPU Design Centre. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly... Come and join a team of extraordinary experts driving significant technology innovation within one of the world’s great companies. The Design Verification Engineer will be responsible for the pre-silicon RTL verification of blocks in low power embedded graphics cores. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. A strong computer architecture background, preferably in graphics, and a foundation in verification methodology will be used to close testing coverage with high confidence. You will have the following experience:

Key Qualifications

  • Expertise with verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman experience is a plus.
  • Expertise with HDL simulators and waveform viewers.
  • Experience defining coverage space, writing coverage model, analyzing results.
  • Experience working under strict schedule deadlines with the ability to run multiple priorities.
  • Graphics architecture and programming (OpenGL/OpenCL) would be a plus.
  • Strong knowledge of computer architecture, general purpose microprocessor and memory sub-system micro-architecture in lieu of graphics experience.
  • Experience with Perl, Shell scripting, Makefiles, TCL a plus.
  • Excellent communication and interpersonal skills combined with the ability to collaborate.

Description

Develop verification plans in coordination with design leads and architects. Build and maintain verification test bench components and environments. Generate directed and directed random tests. Run simulations and debug design and environment issues. Create functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a perfect verification flow.

Education & Experience

BS/MS CE or EE

Additional Requirements