Pixel IP - Front-End Implementation & Integration Engineer
Cambridge, Cambridgeshire, United Kingdom
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. The Hardware Design team at the Cambridge Design Centre works on complex, large-scale media IPs. We partner with our architecture, functional verification, DFT and physical design teams to deliver high quality media IP in order to meet performance, feature, timing, area, and power goals. In this role, you will be responsible for all phases of ASIC front-end logic design, with the primary focus on RTL to synthesis gate-level netlist creation.
- Hands on experience in ASIC front-end design synthesis of complex and high speed IPs to achieve efficient Power, Performance and Area (PPA) goals.
- Proficient in timing analysis, Verilog/VHDL, formal logic equivalence and lint checks
- RTL Integration experience is highly desirable but not mandatory
- Proficient in multi-clock and multi-power-domain designs.
- Deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure.
- Professional experience with ECO implementation, both functional and timing closure.
- Good to have some familiarity with simulation, debugging tools, and working closely with DV team.
- Familiarity with DFT insertion, and multi-mode timing constraints.
- Familiarity with scripting and programming experience using several of the following: Perl/Python, C/C++, and TCL/Bash
- Experience working on Media IPs (ISP/Display Processor/Video Encoding), CPUs, GPUs, or DSPs is desirable but not mandatory
- Ability to work well in a team and be productive under tight schedules.
- Excellent communications skills, self-motivated and well-organised.
You will own the media IP synthesis & RTL Integration work and work closely with Core RTL and PD team to achieve a PPAS (Power, Performance, Area and Schedule) efficient FE implementation work. You will need to run various RTL QC like Synthesis, Lint, CDC, RDC, LEC, UPF etc. to achieve desired QoR. Work with DV/DFT/PD/STA team for debugging, DFT, efficient floor planning, timing closure and power/voltage gating aspects of the design. Work with CAD team for successful deployment of new or improved CAD flows for FE implementation.
Education & Experience
BSc/MSc/BEng/MEng/PhD in related field
- Some international travel required.