Design Verification Engineer (Pixel)

Cambridge, Cambridgeshire, United Kingdom
Hardware

Summary

Posted:
Role Number:200179667
Do your life’s best work here - with the whole world watching. Join a rapidly growing team at our UK design centre. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly... Come and join a team of extraordinary experts driving significant technology innovation within one of the world’s great companies. Work on verifying Apple's camera subsystem, which is done in multiple levels from block level (dozens of TBs), DMA to various top level TBs, with each level of verification provides its own challenges. Our TBs are highly automated with extensive common infrastructure to allow for quick bringup and coverage closure time. Part of the ISP DV includes multi-layered performance testing from block level thru DMA and up to top level based usecases.
In addition, we have a simulation acceleration emulation environment, based the same TB infrastructure as simulation, providing several orders of magnitude of speedup. We utilize a random range of verification methodologies/tools, random, formal, emulation and low power.

Key Qualifications

  • You will have multiple years of relevant experience including:
  • Previous success owning DV for a complex block level
  • Expertise with a verification language such as SystemVerilog/UVM/OVM and/or strong software engineering (C/C++) skills
  • Expertise with Verilog/VHDL, HDL simulators, and waveform viewers
  • Experience defining coverage space, writing coverage model, analyzing results, complex constraints, writing complex TB components (BFMs, scoreboards and checkers etc.) and infrastructure
  • Pixel processing experience is a plus
  • Experience with Perl/Python, Shell scripting, Makefiles, TCL a plus
  • Excellent communication and interpersonal skills and ability to collaborate

Description

You will have full responsibility for DV of a hardware block/IP, including leading a DV team and communicating plans and status to management Develop and track to verification plans on an aggressive schedule through sign-off, in coordination with design leads, architects, and program management Build and maintain verification test bench components and environments Generate directed and directed random tests Run simulations and debug design and environment issues Create functional coverage points, analyze coverage, and improve test environment to target coverage holes Create automated verification flows for block verification Apply knowledge of hardware description languages (VHDL/Verilog), verification languages (SystemVerilog/UVM/OVM), and simulators to verify complex designs Work with other block and core level engineers to ensure seamless verification flow

Education & Experience

•BS/MS CE or EE

Additional Requirements

  • Some international travel will be required.