SoC Back-end Physical Design Engineer - Herzeliya

Herzliya, Israel


Weekly Hours: 42
Role Number:200000152
Imagine what you could do here. At Apple, new ideas have a way of becoming great products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — we continue to strengthen our commitment to leave the world better than we found it. By now the industry is accustomed to Apple taping out the SoCs for our various products at a rigorous pace. In order to achieve this, our world-class design processes are driven by our top-notch Physical Design engineers. Are you a classic partition PnR engineer recognised in the industry for the knowledge in standards and practices in Physical Design? Do you have strong track record with recent successful tape-outs in deep sub-micron technology? As SoC Digital Physical Design Engineer, you will take part in the large scale SoC physical design cycle from netlist to tape-out, including full flow of back-end implementation and verification always meeting schedule and design goals. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products?

Key Qualifications

  • 5+ years experience in physical design of large scale SoC.
  • Extensive experience with one of the place & route tools available today (Synopsys / Cadence).
  • Familiar with hierarchical design approach, top-down design, timing and physical convergence.
  • In-depth understanding of static-timing analysis
  • Extensive know-how in clock/power distribution and analysis, RC extraction and correlation.
  • Experience with PnR platforms coding skills
  • Experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration. Scripting and programming experience using several of the following: Perl, TCL and Make
  • Knowledge in Verilog – advantage.


As a member of our Physical Design team in this highly visible role, you will directly own implementation of design partition(s) (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology. You are going to own block level PnR, floor-planning, clock and power distribution. You will get involved with static timing closure with commercial tools. You will do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC / LVS).

Education & Experience

B.Sc / M.Sc Electric Engineering / Computer Engineering

Additional Requirements