SoC STA engineer
You will be taking part in the Physical Design team as a backend focal point for timing analysis and convergence, working in advanced technologies and interacting closely both with RTL designers, PnR Designers and other top level integration teams.
- 3-5 years experience in STA that includes, but not limited to responsibility for timing and constraints.
- Extensive experience with one of the commercial STA tools.
- Familiarity with hierarchical design approach, top-down design, timing and physical convergence.
- Experience with design synthesis and backend STA closure.
- Deep understanding of designs' constraints development.
- Good understanding of AC timing from specs to implementation.
- Good understanding of DFT modes and their constraints
- Good communication and interaction with Design teams and PD teams.
- Quick learning of flows and methods.
- Advantage - Understanding noise and signal integrity effects.
- Advantage - Timing margins fundamental from synthesis to signoff.
- Advantage - Experience with scripting.
You will be responsible for constraints and timing checkups development, including their delivery for synthesis , PnR and signoff STA. Working in parallel on blocks and chip level STA modes.
Education & Experience