STA and Timing Constraints Development Engineer - Haifa

Herzliya, Israel
Hardware

Summary

Posted: Oct 22, 2018
Role Number: 200000209
You will be taking part in the Design and Integration team as a frontend-backend focal point for all timing and constraints development, working in advanced technologies and interacting closely both with RTL designers and Physical Designers.

Key Qualifications

  • 3-5 years experience in STA that includes, but not limited to responsibility for timing and constraints.
  • Extensive experience with one of the commercial STA tools.
  • Familiarity with hierarchical design approach, top-down design, timing and physical convergence.
  • Experience with design synthesis and backend STA closure.
  • Deep understanding of designs' constraints development.
  • Good understanding of AC timing from specs to implementation.
  • Good understanding of DFT modes and their constraints
  • Good communication and interaction with Design teams and PD teams.
  • Quick learning of flows and methods.
  • Advantage - Understanding noise and signal integrity effects.
  • Advantage - Timing margins fundamental from synthesis to signoff.
  • Advantage - Experience with scripting.

Description

You will be responsible for constraints and timing checkups development, including their delivery for synthesis , PnR and signoff STA. Working in parallel on blocks and chip level STA modes.

Education & Experience

B.Sc, EE/CE

Additional Requirements