Formal Verification Engineer
Will you help us design future generations of revolutionary Apple products? Are you an engineer with a strong foundation and real passion for building new technologies?Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. Are you passionate about changing the world? We have a critical impact on getting high quality functional products to millions of customers quickly. In this highly visible role, you will be responsible for taking part of a SoC Formal verification process of a large scale SoC.
- Advanced knowledge of digital logic design and verification techniques Developed formal property proofs Solid understanding of formal verification technologies and abstraction techniques.
- Knowledge and experience in interpreting hardware specifications and using temporal logic assertion-based languages.
- Advantage: Experience with System Verilog Assertions (SVA) Proficiency in TCL/Perl with excellent debugging skills. Strong team player, excellent communication skills and ability to collaborate.
Formal design verification of System-on-a-Chips (SoC’s), with a critical impact on getting high quality functional products to millions of customers quick.
Education & Experience
B.Sc. in Electrical/Computer Engineering, Computer science or M.Sc/Phd in Mathematics is required.