Senior Formal Verification Engineer
Are you in the Formal Verification domain, interested in developing proofs on the most critical parts of Apple products? Keep reading! Our team is a small family of FV enthusiasts with varied academic backgrounds, seeking for breakthrough methodologies. We encourage professional development and knowledge sharing on regular basis. We constantly aim to stretch our limits, with emphasis on tackling the space explosion problem as well as raising confidence in proof completeness. Sounds you could fit? Let’s talk!
- +4 years FV engineering
- Model checking researchers/developers
- SVA/Jasper - advantage
In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence.
Education & Experience
B.Sc. in Mathematics and Computer Science, Electrical/Computer Engineering, M.Sc/PhD Mathematics