Analog Mixed-Signal Verification Lead
Would you like to join Apple’s growing analog - mixed signal design team? Do you thrive on pushing the simulation and modeling limits of highly complex PHY in advanced technology nodes? Our team is responsible for all aspects of AMS IP development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level. In this technical, hands-on management role, you will be leading a team in charge of every aspect of a AMS PHY verification from modeling to pre-silicon RTL verification of subsystems including MAC, PHY, interfaces and mixed signal digital controls for PLLs, ADCs and DACs.
- 7+ years of industry verification experience with RF/Mixed-Signal blocks, RTL Digital Verification for highly integrated transceivers and SOC verification.
- Team spirit, excellent communication skills and demonstrated capability to lead a team to success.
- Deep understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, parasitic back-annotation, gate level simulation, logic equivalence checking, lower power design flow, etc.
- Expertise building Mixed-Signal testbenches, checkers and tests.
- Expertise creating and using real-numbered analog behavioral models in SystemVerilog or other language.
- Experience in HVL and HDL (SystemVerilog, Verilog)
- Experience with one or more of the following is a plus: embedded CPUs, bus fabric (AXI/AHB/APB), DMA, serial interface design (I2C, SPI, UART), wireless protocols, power management, signal processing.
- Familiarity with ASIC test methodology and knowledge of techniques such as scan insertion, memory BIST and test pattern generation is required.
- Strong verification skills in problem solving, constrained random testing, and debugging.
Take responsibility for all aspects of Analog mixed signal employed by the team and ensure the application of uniform standards and adoption of best practices. Lead the AMS verification team and take responsibility for hiring, resource planning, scheduling, performance management, communication with upper management and overall design team execution. Build block / subsystem / chip level testbench using best in class DV methodology. Review specifications, extract features, define and execute analog mixed signal verification plan. Develop top/block level AMS testbenches, and generate directed/ constrained random tests in a UVM framework. Build and reuse real numbered analog behavioral models, monitors, and checkers for Mixed-Signal blocks. Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage. Write scripts for automation of flow and implement their use.
Education & Experience
BSEE is required. MSEE is preferred.