Clocking Engineer

Herzliya, Israel
Hardware

Summary

Posted: Oct 22, 2018
Role Number: 200000309
Imagine what you could do here at Apple? Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. As a senior member of Apple’s clocking team, you will lead multiple projects working on the newest technology nodes to craft elite clocking solutions for next generation SoC. This is a dynamic work environment with endless learning opportunities working within the design team with members of integration, CAD, circuit and technology engineering

Key Qualifications

  • 5+ years experience in clock distribution design of deep Sub-Micron technologies and CMOS circuits used in high performance SoCs and capacity mentoring, overseeing and delegating work among clock designers,
  • Experience in designing low skew, low power clock distribution networks and clock circuits, IPs.
  • Deep Understanding of analog and mixed-signal IP such as DDR, PLL, DLL, PCIE, ADC, MIPI, Audio
  • Strong Knowledge in different technology nodes.
  • High-level experience in chip floor-planning, standard cell planning and digital timing closure
  • Should be familiar with issues of RC delay, electro-migration, self-heating, aging, and cross capacitance.
  • High-level proficiency in interpretation of extraction, hspice etc. reports.
  • Knowledge of PISI and Lab measurement is a plus
  • Scripting skills in PERL etc. are considered a plus, but not required.
  • Excellent communication skills and able to work with multi-functional teams

Description

As a clock lead of the SoC, you will develop leading clocking solutions for CPU, GPU, SOC, RF, Analog, custom clocks. You will be responsible for Designing and developing clock distribution network for SoCs used in Apple mobile products. Some key responsibilities are listed below: Clock Methodology for clock uncertainty for timing closure, PD clock implementation Clock circuit/IP design including clock duty-cycle corrector, low-jitter clock cells. Clock cost Estimation, Budgeting and verification Clock silicon validation Clock Verification Requirements for CAD, PD etc. Clock Verification and Sign-offs Working with various teams to understand the challenges and needs for clocks Hands-on clock verification using spice, Matlab

Education & Experience

BS.c \ MS.c in Electrical Engineering

Additional Requirements