DV/RTL AMS Design Engineer
The DV/RTL Engineer in the AMS team, is the enter of a PHY design effort collaborating with architecture, CAD, timing and PD design teams, with a critical impact on delivering elite PHY designs. You will also collaborate with the engineering design team to develop the verification environment for block and SoC developments. YOUR RESPONSIBILITIES INCLUDE: Participate in the architecture of next generation PHY. RTL implementation of the micro-architecture. Participate in clearly defining specification, testing and verification of the PHY design. Work in collaboration with CAD, PD teams to implement RTL design into GDS. Run various design verification flow and provide guidelines to other designers. Participate in establishing CAD and design methodologies for correct by construction designs Assist in flow development for PHY integration.
- Requires at least 5+ years of industry experience
- Developing and implementing AMS PHY.
- Advanced knowledge of standard ASIC verification flows including simulation and testbench development.
- Knowledge about industry standards and practices in PHY Design, including RTL writing, verification tools of RTL.
- Deep Understanding of all aspects of PHY construction, Integration and Physical Design.
- Developing block level and SoC test benches around the UVM/OVM methodology.
- Working knowledge of Extraction and STA methodology and tools.
- Excellent knowledge of System Verilog, Verilog.
- Good knowledge of C / C++
- Experience with either Perl/Tcl scripts.
- Knowledge of industry standard interfaces and experience with multiple frontend simulators/debuggers.
- Deep understanding of Design methodology to debug issues at PHY level.
- A teammate with excellent interpersonal skills and the desire to pursue diverse challenges.
Work closely with the design teams in order to review and understand specifications, architecture and microarchitecture. Develop test bench environment(s) and both directed and random/constrained random tests. Come up with functional coverage metrics. Work with other DV teams within Apple to identify holes in the DV flow and implement corrective action. Run RTL and gate simulations and debug/triage failures. Work with designers to develop coverage waivers to achieve 100% code coverage.
Education & Experience
BS.c / MS.c EE or BS.c / MS.c CE