CAD Engineer – Design Verification
Will you help us design future generations of revolutionary Apple products? Are you an engineer with a strong foundation and real passion for building new technologies? Imagine what you could do here. At Apple, new ideas have a way of becoming outstanding products, services, and customer experiences very quickly. Every single day, people do amazing things at Apple. Do you want to impact billions of users by developing extraordinary products with a prime focus on accuracy and performance of the product? You will become part of a hands-on development team that furthers engineering excellence, creativity and innovation. Dynamic, inspiring people and innovative technologies are the norm here. We want you to join our team if you are an innovative engineer with the dream to research and develop solutions that do not yet exist. As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple’s silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your experience and insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple’s DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems.
- You have 5+ years of experience in Verilog and SystemVerilog;familiarity with VHDL a plus.
- Must be very experienced with Synopsys VCS, NC-Verilog, or Modelsim.
- Strong scripting abilities in PERL are needed; TCL or Python is a plus.
- Good communications skills are required and prior customer support experience is a plus.
- Experience writing or maintaining the script or Makefile that builds the simulation Program from RTL is a plus. Familiarity with Verdi and/or DVE is considered a plus.
- Knowledge at C and C++ is a plus.
You will Develop, maintain, and enhance an existing system for regressing RTL. Role involves debugging vendor tool problems. Interacting with DV team to help solve their problems. Implement new functionality to solve emerging problems or to optimize already existing methods.
Education & Experience
BSc/ MSc in Electrical Engineering or Computer Science.