ASIC Design Lead - Herzliya

Herzliya, Israel


Role Number:200000332
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an exceptionally talented IP design lead. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day.

Key Qualifications

  • 10+ years’ experience in digital logic design
  • A proven track record of high-performance designs in high volume production for low power applications
  • Experience in driving micro-architecture and developing specification for logic designs
  • Proven track record of RTL design on large complex IP
  • Experience with system design methodologies that contain multiple clock domains
  • Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on-time
  • Familiarity with all front-end tools including lint, CDC, synthesis is a plus
  • Good understanding on timing/area/complexity tradeoffs on complex interface design
  • Experience in low-power design issues, tools, and methodologies including UPF power intent specification is highly desired
  • Experience in integrating Mixed Signal macros is highly desired
  • Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company
  • Ability to work well in a team and be productive under tight schedules


You will be responsible for the following: - Work with architecture team to define the IP microarchitecture microarchitecture spec. - Refine the spec with reviews with other teams - Develop RTL design of the IP following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design. - Work and collaborate with other designers in the group to deliver results. - Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block - Work with front-end synthesis/STA teams to ensure timing for the block is met - Work with power/performance and functional verification team to ensure high quality of the block - Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process - Work with post silicon validation groups to ensure the IP meets the power/performance targets

Education & Experience

B.Sc. / M.Sc. Electrical Engineering

Additional Requirements