Analog-Mixed-Signal Physical Design Engineer
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented Physical Design Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. In this role, you will be at the center of a PHY design effort interfacing with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class phy designs.
- The ideal candidate will have 5+ years of DDR PHY Physical Design experience on high performance, low power SOC.
- Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floorplaning, and Place & Route.
- Experience in developing and implementing Powergrid and Clock specifications.
- Solid Understanding of all aspects of Physical construction , Integration and Physical Verification.
- Working Knowledge of Basic SoC Architecture and HDL languages like verilog to be able to work with logic design team on timing fixes.
- Power user of industry standard Physical Design & Synthesis tools.
- Solid Understanding of scripting languages such as Perl/Tcl.
- Working knowledge of Extraction and STA methodology and tools.
- Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
As a Physical Design engineer you will be involved with all phases of physical design of high performance phy design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Generate block/chip level static timing constraints. Create full chip floorplan including pin placement , partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs Assist in flow development for chip integration
Education & Experience
BS.c in EE or MS.c in EE