Static Timing Analysis Engineer (STA) – PHY

Haifa, Israel
Hardware

Summary

Posted: Oct 22, 2018
Role Number: 200000361
Join Apple’s - In this highly visible role, as part of a talented team you will be at the heart of the PHY design effort collaborating with all disciplines with critical impact in getting functional products to millions of customers quickly.

Key Qualifications

  • The position requires thorough knowledge of the ASIC design timing closure flow and methodology. You will have the following background:
  • At least 5+ years hands-on experience in ASIC timing constraints generation and timing closure
  • Expertise in STA tools (such as Primetime) and methodologies for timing closure with a deep understanding of OCV, noise and cross-talk effects on timing
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced process technology nodes (28nm and below)
  • Knowledge of timing corners/modes and process variations
  • Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs
  • Proficient in scripting languages (Tcl and Perl)
  • Strong interpersonal skills are a pre-requisite as you will collaborate with a lot of diverse groups (e.g. digital design, verification, DFT, physical design, etc.).
  • Self starter and highly motivated
  • Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools

Description

PHY level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation) Develop and maintain methodology and flows related to timing verification and closure Generation of block timing constraints Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure Support digital chip integration work and flows

Education & Experience

BS.c in EE is required. MS.c in EE is preferred.

Additional Requirements

  • ERPVLSI2018
  • IL_SoC_DV