Junior Formal Verification Engineer
We’re looking for talented university recently graduates, with real passion for Logic design and/or Mathematics, to join our unique formal verification team. We’re offering formal verification course for learning the theory and practice from our leading industry experts. Formal verification (FV) means proving that a property holds for a model of a design. Proving is done exhaustively for all possible cases. FV can be applied to verify SW or HW, our focus is on verifying HW (RTL) using Model checking techniques
- Excellent graduates from leading universities
- analytical thinking
- Highly motivated.
In this role you will be responsible for applying model checking techniques, to find bugs in RTL and architecture specifications
Education & Experience
B.Sc. in Electrical/Computer Engineering, Computer science or M.Sc/Phd in Mathematics