Depth-Sensing Design & Integration Team leader - Herzliya

Herzliya, Israel


Role Number:200058023
Will you help us design future generations of revolutionary Apple products? Are you an engineer with a strong foundation and real passion for building new technologies? Imagine what you could do here. At Apple, new ideas have a way of becoming outstanding products, services, and customer experiences very quickly. Every single day, people do amazing things at Apple. Do you want to impact billions of users by developing extraordinary products with a prime focus on accuracy and performance of the product? You will become part of a hands-on development team that furthers engineering excellence, creativity and innovation. Dynamic, inspiring people and innovative technologies are the norm here. We want you to join us if you are an innovative engineer with the dream to research and develop solutions that do not yet exist. As a Depth-Sensing ASIC Design team leader, you will lead team collaborating with other engineering teams and developing image/signal processing IPs. This is a technical, hands-on management role.

Key Qualifications

  • This position requires in-depth knowledge of the chip micro-architecture and digital logic design.
  • Lead the design team, including taking responsibility for hiring, resource planning, scheduling, communication with upper management and overall design team execution.
  • Take responsibility for performance management of individual team members including goals management, performance evaluations, promotions and disciplinary actions as required.
  • A proven track record of high-performance designs in high volume production for low power applications.
  • Experience in driving microarchitecture and developing specification for logic designs.
  • Proven track record of RTL design on large complex designs.
  • Experience with system design methodologies that contain multiple clock domains.
  • Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on-time.
  • Familiarity with all front-end tools including lint, CDC, synthesis is a plus.
  • Good understanding on timing/area/complexity tradeoffs on complex interface design.
  • Experience in low-power design issues, tools, and methodologies including UPF power intent specification highly desired.
  • Strong communication skills are a must, as the candidate will collaborate with a lot of different groups within the company.
  • Ability to work well in a team and be productive under tight schedules.
  • 10 years of industry experience in an ASIC design role, out of which at least 3 years in a management role.


Manage a team of design and integration engineers to develop and deliver image/signal processing design subsystems and IPs. Work with architecture team to define the design microarchitecture hierarchy and interfaces and develop microarchitecture spec. Refine the spec with reviews with other teams Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design Work with front-end synthesis/STA teams to ensure timing for the IP modules are met Work with power/performance and functional verification team to ensure high quality of the IP Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process

Education & Experience

B.Sc degree or higher in EE/CS/CE from a leading university

Additional Requirements