STA manager

Herzliya, Israel


Role Number:200062574
Will you help us design future generations of revolutionary Apple products?Are you an engineer with a strong foundation and real passion for building new technologies? Imagine what you could do here. At Apple, new ideas have a way of becoming outstanding products, services, and customer experiences very quickly. Every single day, people do amazing things at Apple. Do you want to impact billions of users by developing extraordinary products with a prime focus on accuracy and performance of the product? You will become part of a hands-on development team that furthers engineering excellence, creativity and innovation. Dynamic, inspiring people and innovative technologies are the norm here. We want you to join us if you are an innovative manager with the dream to research and develop solutions that do not yet exist

Key Qualifications

  • - Thorough knowledge of the ASIC design timing closure flow and methodology.
  • - 7+ years’ experience in ASIC timing constraints generation and timing closure. Expertise in STA tools (Primetime) and flow
  • - 2+ years managerial experience is and advantage
  • - Knowledge of timing corners/modes and process variations related issues
  • - Proficient in scripting languages (TCL and Perl)
  • - Familiarity with RTL2GDS flow
  • - Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing
  • - Expertise in Timing closure methodology
  • - Self-starter and highly motivated


As an ASIC Integration Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project cycle (physical implementation) Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.

Education & Experience

BSEE/MSEE, EECS, or CS is required.

Additional Requirements