Standard Cell Design Engineer
Tel Aviv, Israel
Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? Do you have a passion for crafting entirely new solutions? Do you love building without precedent? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Standard Cell Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact delivering products to market quickly.
- 5+ years of experience in Standard Cell Library development and Quality Assurance.
- Knowledge of standard cell layout, DRM, DRC/LVS decks, PDV flows, Virtuoso.
- Design experience in deep submicron technologies with understanding of layout rules.
- Familiarity of flop and complex Standard Cells design.
- Experience in scripting in Perl and/or TCL.
- Knowledge of SKILL coding.
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of talented engineers. As a Standard Cell Design Engineer for the custom circuits team, you will perform the following: - Develop standard cells to improve design PPA. - Develop optimal power switch cells that cater to today’s Low Power Design Requirements. - Engage with CPU, SOC and GPU teams on chip level integration requirements. - Responsible for Virtuoso library releases for custom design use. - Work with foundries on DRM complaint layout checkers and iPDK requirements. - Manage layout migration to new PDK, PDV of library cells, digital library releases.
Education & Experience
BSEE / MSEE is required.