Design Verification Engineer
changing the game? We have an opportunity for an exceptionally talented design verification engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. This role is for a digital DV engineer who will enable us to produce fully functional first silicon. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development, sign-off for RTL freeze and tape-out.
- Deep knowledge of System Verilog and UVM
- Advanced knowledge of System Verilog and UVM
- Experience developing UVM based IP test-benches
- Experience with complex designs and advanced debug skills ability
- Experience with verification tools such as simulators, waveform viewers, build/run automation, coverage collection and analysis, gate level simulations
- Experience with serial protocols such as PCIe or USB
- Proven knowledge of one of the scripting languages: Python, Perl, TCL
- In lieu of UVM knowledge, C/C++ experienced level knowledge
- Lab hands-on debug
of the IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. Develop block, IP and SoC level test-benches Track and report DV progress using a variety of metrics, including bugs and coverage.
Education & Experience
BSc or MSC in Electrical Engineering