SoC Power UPF Methodology and Implementation Engineer
As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Power UPF Engineers. The SoC hardware development team is looking for a Power UPF engineer who will drive IP and chip-level power intent-UPF definition, implementation & verification on cellular SoCs.
- We are looking for applicants with experience in ASIC design methodology and an emphasis on power definition.
- Experience in ASIC design flows.
- Familiar with power intent definition, implementation, and verification flow.
- Knowledge of scripting languages like Tcl, Perl, and Python.
- Familiar with power analysis and optimization methods.
- Familiar with entire RTL2GDS flow (RTL sim, equivalence, synthesis, P&R, intent checking)
- Strong communication skills are a pre-requisite as you will collaborate with a lot of different groups.
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas. The main responsibility of this role is to develop and support IP-level and chip-level power intent-UPF definition, implementation, and sign-off for digital and mixed-signal designs, including: Drive IP power intent definition, implementation, and verification. Drive coverage of power intent across static and dynamic checking methodologies. Bring up power intent checking flows on new projects. Drive power intent sign-off for tape-out. Liaison with CAD and physical design verification team for debugging any power intent flow issues.
Education & Experience
BSsMSs or Computer Science required.