Digital Verification Engineer - Imaging & Sensing Technology Group

Herzliya, Israel


Role Number:200369345
Apple designs consumer electronics that have touched millions and changed Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple products. Do you love working on challenges that no one has solved yet? Our group developes depth sensing systems such as the revolutionary True Depth camera that powers Face ID. This multi-disciplinary group of engineers is responsible for architecture, design, and development of these highly sophisticated sensing systems for all Apple products. This role is for a Digital Verification Engineer who will enable us to produce fully functional camera sensors. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Key Qualifications

  • 3+ years of experience in digital logic design verification
  • Basic knowledge of SystemVerilog and UVM
  • Experience developing UVM based IP test-benches
  • Experience with complex designs and advanced debug skills
  • Experience with verification tools such as simulators, waveform viewers, build/run automation, coverage collection and analysis, gate level simulations
  • Strong interpersonal skills are a must, as the candidate will communicate with a lot of diverse groups within the company
  • Ability to work well in a team and be productive under tight schedules
  • Good knowledge scripting languages: Python, Perl, Tcl
  • Preferred:
  • Experience with developing behavioral models for analog/mixed signal blocks
  • Knowledge of formal verification methodology
  • In lieu of UVM knowledge, e Specman or C/C++ experienced level knowledge
  • Experience with Lab hands-on debug


In this role, you will be responsible for ensuring bug-free first silicon for part of the IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop behavioral models for analog / mixed signal blocks such as PLL/DLL, A/D and D/A converters, custom logic cells etc. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling all features under your care, and debug of the test failures. Develop block, IP and chip level test-benches. Supervise and report DV progress using a variety of metrics, including bugs and coverage.

Education & Experience

BSc or MSc in Electrical Engineering or Computer Engineering

Additional Requirements