We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.
- 3-5 years experience in STA that includes, but not limited to responsibility for timing and constraints.
- Extensive experience with one of the commercial STA tools.
- Familiarity with hierarchical design approach, top-down design, timing and physical convergence.
- Experience with design synthesis and backend STA closure.
- Deep understanding of designs' constraints development.
- Good understanding of AC timing from specs to implementation.
- Good understanding of DFT modes and their constraints
- Good communication and interaction with Design teams and PD teams.
- Quick learning of flows and methods.
- Advantage - Understanding noise and signal integrity effects.
- Advantage - Timing margins fundamental from synthesis to signoff.
- Advantage - Experience with scripting.
You will be responsible for: Develop/support automated block and full chip level signoff flows Full Chip Timing/Noise convergence and full signoff for high quality TO Enable hierarchical Timing flows Power optimizations Generate block level budget and context for correlation with Full Chip Drive custom IP integration and custom timing checks flows Close work with Design, DFT, architecture and Power team
Education & Experience