Mixed-signal IP Shared Library Design and Management Engineer
Santa Clara Valley (Cupertino), California, United States
The analog and mixed-signal team within Apple silicon engineering designs ground breaking IPs for high-speed communication, clocking and metrology that are used in every chip designed at Apple! We are looking for engineers to identify re-use scenarios for sub-blocks, factor designs when needed and help efficiently manage the shared design/model libraries across a variety of projects!
- Excellent knowledge of coding in Verilog/SystemVerilog
- Excellent knowledge of version controls systems such as Perforce
- Good understanding of digital logic, systems and simulation
- Good comprehension of hardware IP management
- Good understanding of coding and scripting in languages like C/C++/PERL/Python
- Familiarity with hardware design flows such as functional verification, synthesis, equivalence checking, and lint
- Familiarity with specific blocks like PLLs and High-speed Serial IO is a plus
In this job you will have to work with the mixed-signal IP design teams to identify and factor IPs for re-used blocks and place them in shared libraries. You will have to work with the design verification team to ensure the right checks are in place for constant updates of these libraries. You will also have to devise efficient methods to deliver/track updates to various consuming chips.
Education & Experience
BS/MS in EE/CS with minimum of 5 years of relevant industry experience