VLSI CAD Engineer - Logic Equivalence & ECO

Santa Clara Valley (Cupertino), California, United States
Hardware
Submit CVVLSI CAD Engineer - Logic Equivalence & ECO
Back to search results

Summary

Posted:
Role Number:200507870
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Hardware Technologies group, you’ll help design and validate our next-generation, high-performance, power-efficient system-on-chip (SoC) designs. You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices!

Key Qualifications

  • Exposure to programming languages, such as Perl, Python, and TCL
  • Relevant VLSI design course work including Digital Design, Microarchitecture Design, Synthesis, Simulation, FPGA development.
  • Prior Internship experience with equivalence checking and/or synthesis tools
  • Course work / project experience writing RTL (Verilog, SystemVerilog, or VHDL)
  • Excellent communication skills, including previous customer support experience
  • Excellent interpersonal skills, including collaboration, inclusivity, active listening, and a growth mindset.

Description

As a member of the CAD Team, you will develop, maintain, and enhance logic equivalence checking flows. You will support the software and scripts that design teams are using to verify implementation flows and complete ECOs. You will get to explore the possibility of applying machine learning techniques to improve logic equivalence tools and flows. You will work directly with EDA vendors to address tool issues. Core Responsibilities: - Develop, maintain, and enhance CAD applications for logical equivalence. - Interact with the Integration team to understand their problems and propose solutions to solve them. - Support frontend design closure , ECO verification, and flow signoff. - Triage and solve CAD flow problems, and working around 3rd party EDA tool problems. - Collaborate with other CAD engineers to integrate your solutions into their flows.

Education & Experience

Minimum requirement of Bachelors Degree + 0 years of relevant industry experience.

Additional Requirements

Pay & Benefits

  • At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $55.81 and $84.08/hr, and your base pay will depend on your skills, qualifications, experience, and location.

    Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

    Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Submit CVVLSI CAD Engineer - Logic Equivalence & ECO
Back to search results
See all roles in Santa Clara Valley (Cupertino)