Design Verification Engineer
Tokyo, Tokyo-to, Japan
The people here at Apple don’t just build products — they build the kind of wonder that’s revolutionized entire industries. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do, from amazing technology to industry-leading environmental efforts. Join Apple, and help us leave the world better than we found it. Imagine what you could do here. As a member of design verification team, you will have the responsibility for construction of verification environments, coding of test scenarios and assertions. In this capacity, your role will involve close collaboration with analog and digital design engineers.
- Typically requires a minimum of 5 years of experience in System Verilog or other verification language
- Knowledge of constrained random verification environments.
- Hands-on experience with Assertion Based Verification
- Basic design background in support of verification results analysis.
- Knowledge with Object Oriented Programming
Construction of verification environment by using Verilog, System Verilog or UVM Designing test plan for verification Coding test scenarios, assertion and debugging for Digital Design
Education & Experience
- Knowledge of one of verification language (UVM, OVM, or VMM).
- Familiarity with system design using C(C++) or Verilog.
- Hands-on experience with formal verification (assertion-driven verification).
- ATE functional test pattern generation for logic testers.