Sr. VLSI CAD Engineer - Timing for Gate-Level Flows & Methodologies

Beaverton, Oregon, United States


Role Number:200302774
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you will help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you will be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices! In this highly transparent role as a senior level member of the STA CAD Tech & Signoff team, you will be an integral part of the effort to improve the performance of Apple silicon. You will be responsible for all aspects of timing including working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure.

Key Qualifications

  • Typically requires 8+ years of hands on experience in static timing analysis flows.
  • Familiar with all aspects of STA of large high-performance SoC or Processor designs in deep sub-micron technologies.
  • Proficiency in analysis, tools, and methodologies for timing closure.
  • Deep understanding of noise, cross-talk, OCV effects, margins, and constraints.
  • Programming in Perl, Python, Tcl, C++ or other languages is a must.
  • Good communicator who can accurately assess and describe issues to management as well as follow solutions through to completion.
  • Familiarity with timing and power ECO techniques and implementation, circuit modeling, including SPICE models and worst-case corner selection is a plus.
  • Familiarity in distributed/scalable software development life cycles, including documentation and testing.


- Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure. - Facilitate and drive STA methodology changes to improve overall STA flows. - Create/maintain scripts and methods for timing analysis and power reduction. - Deep analysis of timing paths to identify key issues. - Implement infrastructure/scripts to facilitate large scale timing reports mining and visualization. - Help build timing and power ECO custom scripts for project tapeout. - Work with Physical Design team, highlighting issues and standard methodologies. - Document and help with guidelines/specs.

Education & Experience

Bachelor's or Master's degree in a technical field is required

Additional Requirements