ASIC Design Engineer - Cache
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a talented engineer to join our exciting team of problem solvers. Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on designing special purpose cache and controller which is part and parcel of the SOC memory hierarchy
- The ideal candidate will have 5+ years of ASIC design experience:
- - 5+ years of development of memory system.
- - 5+ years of RTL/micro-architecture definition.
- - 5+ years of experience in PPA (performance/power/area) analysis.
- - Knowledge of high performance coherent memory system or interconnect architectures.
- - Strong cache design background including good understanding of different memory organizations and tradeoffs.
- - Knowledge of high performance memory subsystem and dram controller.
- Participate in Cache micro architecture development from specifications found from architecture guideline and model analysis. - Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team. - Develop/debug RTL design of different sections of the cache. - Work with physical design team to close timing of the same.
Education & Experience
- MS/PhD in a relevant area