DMS Verification Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200000641
Imagine what you could do here at Apple! Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. The DMS Verification team is searching for a self-motivating, passionate electrical engineer for the role of DMS Verification Engineer. As a member of the DMS team, Apple is looking for a strong candidate who can take on diverse challenges in verifying digital/mixed-signal designs. In this highly visible role, you will be at the center of chip design effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly. You will become part of a hands-on development team that fosters engineering excellence, creativity and innovation. Collaboration across teams is a key component of success at Apple. The right candidate will thrive in that type of environment. You will work with us from Apple's headquarters in Cupertino, California. It's one of the most exciting aspects of the job. Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you help us design the next generation of revolutionary Apple products? Do you have the following qualifications or experience?

Key Qualifications

  • We typically require at least 8 years of experience and we are looking for individuals with validated experience taking chips to production
  • Experience in analog behavior modeling and analog mixed signal simulations
  • Familiarity with Systemverilog, Systemverilog Testbenches, sv2012 Real, UDNs/UDTs, wreal, Verilog-AMS
  • Hands-on experience with Analog Assertion Based Verification
  • Design background to analyze verification results
  • Knowledge of UVM-AMS is a plus
  • Experience writing scripts in languages such as Perl or Python
  • Understanding of analog/mixed-signal blocks like PLL, ADC, DAC
  • Excellent teammate with excellent communication skills


As a DMS Verification Engineer, you will be responsible for performing the verification on digital/mixed signal designs including: - Development of analog behaviour models in Verilog or System Verilog - Verifying analog functions - for example coding test scenarios and environments for analog verification and/or assertion - Working multi-functionally with Analog Designers setting up AMS simulation environment - Supporting mixed-signal co-simulation using Verilog models of analog IP

Education & Experience

MSEE with 8 years of analog verification experience or analog design experience with behavioral modeling

Additional Requirements