Sr. ASIC Design Engineer
Austin, Texas, United States
At Apple, great ideas have a way of becoming great products and customer experiences very quickly. The industry is accustomed to Apple taping out the SOC’s for our various products at a rigorous pace. In order to achieve this, Apple’s world class chip is driven by top notch design engineers who implements various blocks of the chip and deliver high quality components to SoC. This is a high visibility and mission critical role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design.
- This position requires in-depth knowledge of the chip micro-architecture and digital logic design.
- At least 10+ years experience in digital logic design
- A proven track record of high performance designs in high volume production for low power applications
- Experience in driving microarchitecture and developing specification for logic designs
- Proven track record of RTL design on large complex designs
- Solid working experience with synthesis, power, performance and verification team to develop and deliver high quality RTL design on-time
- Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company
- Self-starter, highly motivated, highly organized, and schedule driven is a must
- Familiarity with all front-end tools including lint, CDC, synthesis is a plus
- Knowledge of high speed DRAM memory controller design or interconnect design is highly preferable.
You will be responsible for the following: 1) Work with architecture team to define the design microarchitecture hierarchy and interfaces and develop microarchitecture spec. Refine the spec with reviews with other teams 2) Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design. 3) Work and collaborate with other designers in the group to deliver results. 4) Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block 5) Work with front-end synthesis/STA teams to ensure timing for the block is met 6) Work with power/performance and functional verification team to ensure high quality of the block 7) Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process
Education & Experience
MS/BS in EE, CE or equivalent experience.