IC Packaging Engineer
Santa Clara Valley (Cupertino), California, United States
Do you like to work on groundbreaking technologies that enable amazing new products? Do you have the attention for details and love for excellence to work towards an extraordinary result? We are looking for a talented and passionate IC Packaging Engineer to join our team. In this highly visible role, you will own and drive advanced package selection, new product package structure and configuration optimization. You will be responsible for package/SIP layout, optimization, design verification and taping out.
- Minimum 5+ years hands on experience with Cadence APD/SIP
- Must have good EE fundamentals
- Must have solid signal and power integrity fundamentals
- Experience in package design, design for manufacturing review. Familiar with layout review tools such as CAM350/Valor or Calibre.
- 2D/2.5D and 3D package connection, memory package, stacked die substrate design experience
- Familiar with BGA package substrate technologies
- Experience preferred in schematic capture, layout and design using Cadence Allegro Schematic Design Entry (Concept HDL) design tools is a plus
- Good exposure to Unix environment, scripting languages (PERL, Python, TCL and/or shell) and methodology is a plus
•Interface and coordinate with cross-functional groups throughout Apple on new product package/SIP selection, feasibility analysis and design •Implement the physical design of SIP, SoC and memory chips •Work cross-functionally, understand trade-offs, constraints, and optimizing silicon floor plan, bump and package pin out. •To optimize signal/power integrity of package/SIP design •Drive methodology, innovations, and productivity improvements in package design together with vendors and developers on feature development and bug resolution
Education & Experience
•BS or MS Electrical Engineering, Mechanical Engineering, Materials Science or Physics required and relevant experience within technical discipline. MS or PhD preferred.