Design Verification Engineer

Santa Clara Valley (Cupertino), California, United States


Posted: Oct 22, 2018
Weekly Hours: 40
Role Number: 200000945
Imagine what you could do here at Apple? Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. You will become part of a hands-on development team that fosters engineering excellence, creativity and innovation. Collaboration across teams is a key component of success at Apple. The right candidate will thrive in that type of environment. You will work with us from Apple's headquarters in Cupertino, California. It's one of the most exciting aspects of the job. Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you help us design the next generation of revolutionary Apple products?

Key Qualifications

  • Strong knowledge in C/C++ based modeling in the domains of signal processing, system performance and memory management
  • Strong debugging skill using GDB and Valgrind
  • Experience with integrating model with Verilog, co-simulating and debugging in an integrated environment
  • Strong skill in modeling with floating point arithmetic, parametrized precision
  • Experience in defining and building modular architecture of a model based on a system architecture/design specifications


Work closely with the design team to review specifications and architecture, extract features, define modeling plan, framework  Defining, building and debugging C/C++ based transaction level model Integrate model with the design and test benches and simulate with Verilog simulators Build model debug infrastructure using GDB/Valgrind or with Simulator

Education & Experience

BSEE/MSEE with 10+ years of relevant. PhD Preferred

Additional Requirements