Sr. DFT Design Verification Engineer
Austin, Texas, United States
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As our DFT Design Verification Engineer, you will be working on a small team, which owns the complete DFT pre-silicon verification and support for silicon bring-up of a semiconductor design in an advanced technology node. You'll build and maintain verification test bench components and environments, which is why you should be more than proficient with scripting and System Verilog, as well as be able to come up with test plans for validating IP.
- Experience with verification language such as SystemVerilog
- Experience with Verilog is ideal
- Knowledge of IEEE 1500/IEEE 1149
- Experience with Verdi and debugging problems with waves
- Experience defining coverage space, writing coverage model, analyzing results
- Experience working under strict schedule deadlines with the ability to handle multiple priorities
- Experience with Perl, Shell scripting, Makefiles, TCL
- Experience with Python is a plus
- Excellent communication skills and ability to collaborate
Develop verification plans in coordination with design leads and architects Generate directed and directed random tests Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes Create automated verification flows for block verification Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs
Education & Experience
BS/MS CE or EE or equivalent experience.