Santa Clara Valley (Cupertino), California, United States
As a member of ASIC design team, you will play a central role in driving silicon prototyping utilizing FPGAs. The individual will be responsible for analyzing design spec, develop and implement test plan for major design blocks by generating suitable stimulus and gathering/analyzing result.
- Maintain common design platform for ASIC as well as FPGA, with considerations for memories, I/O Pads, gated clocks and complex generated clocks.
- Design and verification using Verilog/System Verilog
- Perform FPGA Synthesis, Place & Route, timing optimizations
- Perform bring-up, debug, and validation of designs to achieve functional and performance goals
- Create and execute plans to bring-up, debug, and validate designs
- Thoroughly document and support each of above steps
- Collaborate with cross-functional teams in order to define prototype hardware to evaluate new technologies and features
Typically requires a minimum of 6 years of experience with bring up, debugging and verification on FPGA In depth experience with FPGA platforms: Xilinx FPGA boards, debug, performance and throughput tuning In depth knowledge of top down FPGA development process Solid understanding of the tool flow from RTL to bitstream Hands on lab bring-up experience, debug, and instrument usage Proven design validation skills Proven micro architecture development and excellent documentation skills In depth experience writing Verilog code. Experience with System Verilog verification environments Good analytical skills Experience on Python script is plus Experience on GUI development is plus Experience on PCIe or USB is plus Experience on HDMI or DisplayPort is plus Experience on video/image processing is plus Excellent oral and written English skills
Education & Experience
BSEE, MSEE with industry experience over 6 years.