SoC Packaging Engineer

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted: Oct 22, 2018
Role Number: 200001004
Seeking an innovative individual to take on Packaging integration and process development role for a variety of projects including SoC.

Key Qualifications

  • 5+ years experience in Semiconductor Packaging Process, Design and Material development.
  • Expert in packaging assembly processes including SMT, die prep, die attach, flip chip, underfilling, wire bonding, molding, singulation and back-end processes.
  • Expert in materials characterization and analysis, DOE, reliability standards and FA techniques.
  • Excellent communication skills that can enable the candidate to work well with internal cross functional teams and overseas suppliers.
  • Ability to work independently and take on projects with minimum supervision.
  • Excellent engineering problem solving with strong physics and fundamentals.
  • Familiar with package design softwares, APD, etc.
  • Working knowledge in memory device architecture, design, test, etc.
  • Strong program management skill

Description

•Responsible to lead packaging assembly technology development. •Work with cross functional team and lead SoC Package integration and architecture efforts. •Work with foundry and OSAT to bring packaging solution from concept to HVM. •Drive industry with advanced Package solutions, new material development, and specs.  •5 % International travel.

Education & Experience

•Ph.D. or M.S. in Chemical Engineering, Materials Science, Mechanical Engineering, or Physics.

Additional Requirements